Engineer, Defect Reduction & Yield Enhancement
Core
Drive defect reduction and yield enhancement in front-end semiconductor manufacturing by identifying, containing, and eliminating yield-limiting defect mechanisms.
Role type
Senior IC manufacturing quality engineer (semiconductor front-end fab)
Builds
High-yield CMOS/BiCMOS/bipolar semiconductor wafers for autonomous vehicles, drones, factories, AR, and remote healthcare
Domain
Semiconductor manufacturing (Front-End Fab)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Defect control ownership, SPC trend monitoring, correlation/commonality analysis, excursion investigation, Pareto analysis, yield kill ratio analysis, OCAP development, metrology tool support (AOI/SEM), cross-functional problem solving, statistical analysis (t-test, ANOVA), JMP proficiency
Preferred skills
Defect inspection tool experience (KLA/ONTO bright/dark field, Automated SEM), defect-to-sort correlation analysis, spatial signature analysis, KLARITY ACE/PDF DataPower proficiency
Technologies
KLARITY ACE Defect, KLARITY Defect, PDF DataPower, JMP, Automated Optical Inspection (AOI), SEM review platforms
Responsibilities
Monitor SPC trends and support corrective actions for inline excursions; execute defect reduction initiatives using Pareto and yield kill ratio analysis; support defect excursion investigations and containment documentation; maintain out-of-control action plans (OCAPs); support defect inspection and SEM review tool performance; collaborate with Integration, Process, Equipment, and Operations teams to plan experiments and propose process optimizations; analyze defect and yield data and communicate findings
Seniority
Mid-level IC (2+ years experience)