Defect/Integration Engineer
Core
Drive defect reduction and yield improvement projects for specific layers in a semiconductor wafer fab, utilizing data analysis and statistical process control to identify root causes and implement robust fixes.
Role type
Senior IC defect and integration engineer
Builds
Higher yield semiconductor wafers and improved process stability
Domain
Semiconductor manufacturing (Wafer Fab)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Root cause analysis, Statistical Process Control (SPC), Data analysis (Klarity, SAS, JMP, ACE), Design of Experiments, Cross-functional collaboration, Project management
Preferred skills
Python programming, SEM & FIB analysis, Wafer cross-section interpretation (FIB, SEM, TEM, EDX)
Technologies
Klarity Defect, SAS, JMP, ACE, Python, SEM, FIB, TEM, EDX
Responsibilities
Monitor inline defects using SPC to control process limits and detect excursions; Investigate complex technical challenges to identify underlying causes of defects; Collaborate with process, equipment, and quality teams to resolve issues and prevent reoccurrence; Maintain and improve inspection recipes to balance nuisance detection with high capture rates; Lead defect reduction projects from scoping to completion using Pareto analysis.
Seniority
Senior, hands-on IC