Staff Engineer, Digital Design Engineering (AI/ML)
Core
Develop complex digital subsystems within mixed-signal and power management ICs while applying AI/ML techniques to improve design automation, optimization, and productivity.
Role type
Staff Digital Design Engineer (AI/ML)
Builds
Mixed-signal and power management ICs
Domain
Semiconductor / Digital IC Design / AI/ML
Deliverable
production ML models | product features
Required skills
RTL design in Verilog/SystemVerilog, AI/ML application for design automation, Python scripting, static timing analysis, synthesis, DFT methodologies, Cadence tools (Genus, Innovus, Tempus, Conformal), clock domain crossing analysis
Preferred skills
Place-and-route techniques, low-power design (multi-voltage, power gating, UPF), mixed-signal SoC integration, formal verification
Technologies
Verilog, SystemVerilog, Python, Tcl, Genus, Innovus, Tempus, Conformal, Cadence
Responsibilities
Apply AI/ML to improve synthesis results, timing closure, and power estimation; Develop and implement digital subsystems including control logic and on-chip processing blocks; Execute RTL design, coding, and optimization for performance, area, and power targets; Perform synthesis with timing and placement constraints and static timing analysis; Participate in architecture and design reviews; Collaborate with analog design teams to integrate digital-analog interfaces
Seniority
Staff, hands-on IC design with strategic impact