Defect Reduction Engineer
Core
Support defect control and reduction in a high-volume 24x7 semiconductor manufacturing environment to achieve yield and performance goals.
Role type
Defect Reduction Engineer
Builds
Inline inspection strategies, FCC trend monitoring plans, and defect data analysis for new technology introductions and legacy production nodes.
Domain
Semiconductor manufacturing (Foundry)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Semiconductor process engineering, defect monitor and reduction, SPC methodology, DOE methodology, data mining, troubleshooting, cross-functional collaboration
Preferred skills
Leading logic technology development (45nm or below), advanced defect inspection tools (bright field, dark field, e-beam, Vis-edge), Klarity Defect software
Technologies
Klarity Defect, bright field, dark field, e-beam, Vis-edge
Responsibilities
Support New Product Introduction (NPI) by presenting inline inspection strategy and evaluating process changes; Perform fab process/tool trend data analysis to identify root causes and prevent process excursions; Establish FCC and trend monitoring plans for new and legacy technology nodes; Respond to foundry customer requests with data and analysis; Support new technology and process transfer projects from Samsung HQ.
Seniority
Senior, hands-on IC