R&D Engineer Hardware 4
Core
Develop predictive yield and performance optimization tool sets using ML, DL, and GenAI to translate silicon data into actionable strategies for wafer-level yield maximization.
Role type
Principal Machine Learning & Silicon Yield Engineer
Builds
Predictive yield models, performance optimization tool sets, and scalable production data workflows
Domain
Semiconductor manufacturing, silicon architecture, and electronic design automation
Deliverable
production ML models
Required skills
Machine Learning, Deep Learning, GenAI, Python, C++, R, Static Timing Analysis (STA), Spice modeling, SoC telemetry analysis, wafer-level yield prediction, silicon macro characterization, DFM practices, EDA tools
Preferred skills
Experience with Cadence Virtuoso, Primetime STA tools, large-scale database management, anomaly detection, multivariate regression
Technologies
Python, C++, R, Cadence Virtuoso, Primetime, large-scale sensor databases
Responsibilities
Design and deploy ML/DL/GenAI models for yield prediction; organize and analyze multi-source sensor databases; interpret circuit telemetry to isolate failure mechanisms; partner with foundry and DFM teams to drive yield strategies; develop and productize experimental data workflows
Seniority
Principal, hands-on IC with strategy & mentorship