III-V Wafer Fab Process Engineer (Lithography)
Core
Developing, qualifying, and sustaining photolithography and etch processes for III-V compound semiconductor devices (InP, GaAs) to establish robust manufacturing, optimize yield, and support high-volume production.
Role type
Senior IC process engineer (lithography)
Builds
III-V semiconductor devices (InP, GaAs)
Domain
Semiconductor manufacturing (III-V compound semiconductors)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
photolithography process development, process qualification, DOE, SPC, root cause analysis (8D, 5 Why, Fishbone, FMEA), yield improvement, defect minimization, process control documentation
Preferred skills
III-V semiconductor manufacturing experience
Technologies
i-line, DUV (193 nm), aligner/stepper/scanner platforms, photoresist, BARC, lift-off lithography
Responsibilities
Develop and optimize photolithography processes for III-V wafer fabrication; Establish process windows for critical lithography parameters (coating, bake, develop, exposure, focus, overlay, CD control); Qualify new lithography materials and equipment; Monitor process health using SPC and investigate excursions; Analyze yield loss and drive continuous improvement projects; Develop and maintain process documentation (WI, Control Plans, PFMEA, Recipes, ECO)
Seniority
Senior, hands-on IC
