FPGA Development Tools Engineer – Synthesis
Core
Develop and optimize synthesis algorithms to convert RTL designs into efficient gate-level representations for FPGA platforms.
Role type
Senior IC FPGA development tools engineer (synthesis)
Builds
FPGA compiler toolchain and synthesis capabilities
Domain
Semiconductor / Electronic Design Automation (EDA)
Deliverable
production ML models | product features
Required skills
RTL design and synthesis flows, C/C++ for tool development, algorithms and data structures, logic synthesis and optimization techniques, FPGA or ASIC design flows, timing-driven design considerations
Preferred skills
FPGA toolchains (Quartus, Vivado), FPGA architectures (LUTs, DSPs, BRAM), advanced optimizations (retiming, logic restructuring), scripting (Python, Tcl), compiler development, EDA algorithms
Technologies
Verilog, SystemVerilog, VHDL, C, C++, Python, Tcl, Quartus, Vivado
Responsibilities
Design and optimize synthesis algorithms, contribute to FPGA compiler flow integration, improve quality of results (QoR), develop RTL analysis tools, collaborate with cross-functional teams, debug synthesis results, develop internal automation tools
Seniority
Senior, hands-on IC