Staff Engineer - Formal Verification
Core
Identify and verify digital hardware blocks using formal verification techniques to ensure correctness before silicon fabrication.
Role type
Staff Engineer - Formal Verification
Builds
Verified RTL designs for RISC-V processors and digital systems
Domain
Semiconductor / Chip Design / Digital Hardware
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Formal Verification, Formal Abstraction Techniques, Sign-off process, Hardware Description Languages (VHDL, Verilog, SystemVerilog), Formal Verification Tools (VC Formal, JasperGold), Chisel, Scripting/Automation, Debugging RTL
Preferred skills
Object-oriented Programming, Processor architecture knowledge
Technologies
Chisel, VC Formal, JasperGold, VHDL, Verilog, SystemVerilog
Responsibilities
Identify blocks suitable for formal verification, Create formal test plans, Implement and maintain formal verification environments, Apply FV techniques to prove DUT correctness, Debug RTL failures, Guide team members on FV tools, Develop automation scripts, Review formal setups and proofs
Seniority
Staff, hands-on IC with mentorship
