System Validation Engineer (New Grads)
Core
Validate SiFive RISC-V CPUs using FPGA-based platforms and development boards, performing root cause analysis and debug automation.
Role type
Entry-level System Validation Engineer
Builds
Validation workflows and debug scripts for RISC-V CPU hardware and software
Domain
Semiconductor, RISC-V architecture, FPGA validation
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RISC-V architecture, FPGA validation, root cause analysis, Verilog, Python scripting, Linux, JTAG debugging, ILA debugging, logic design, Computer Architecture
Preferred skills
null
Technologies
RISC-V, FPGA, Verilog, Python, BASH, Linux, JTAG, ILA
Responsibilities
Execute root cause and failure analysis for RISC-V CPU hardware/software; Utilize ILA and JTAG debuggers for FPGA troubleshooting; Develop failure hypotheses via systematic elimination; Create Python scripts to automate debug workflows
Seniority
Entry-level, new grad
