System Validation Engineer to Staff Engineer
Core
Develop, deploy, and support emulation and FPGA environments for RISC-V processor and SoC designs to enable silicon bring-up and software readiness.
Role type
System Validation Engineer (FPGA/Emulation)
Builds
RISC-V CoreIP processor designs and SoC architectures
Domain
Semiconductor chip design, RISC-V architecture, FPGA development
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
FPGA platform development, processor and SoC architecture understanding, system validation and debugging, test plan generation, failure analysis, coverage analysis, Linux-based open source software development
Preferred skills
Chisel, Scala, high-level verification flow methodology
Technologies
FPGA, RISC-V, Linux, Chisel, Scala
Responsibilities
Bring up Silicon designs on FPGA platforms, root cause design and emulator environment issues, collaborate on emulation strategies, establish hardware and software readiness for silicon bring-up
Seniority
Mid-level (3+ years experience)
