Director - Ultra Low-latency Trading System Architect
Core
Lead the design and implementation of an ultra-low-latency electronic trading platform targeting microsecond and sub-microsecond latencies.
Role type
Director, Ultra-Low-Latency Trading System Architect
Builds
Electronic trading platform, market data infrastructure, DMA engine, risk enforcement framework
Domain
Financial Markets / High-Frequency Trading / Distributed Systems
Required skills
Ultra-low-latency systems engineering, Distributed systems & deterministic computing, Financial markets & HFT, Message protocol & serialization design, Kernel-level systems programming, Performance engineering & profiling at scale, Systems programming & production operations
Preferred skills
Market data feed handlers & direct exchange connectivity, End-to-end ultra-low-latency system building, Order entry normalization frameworks, Kernel-bypass networking (DPDK, Open Onload), Regulatory audit/compliance experience, Colocation & private fiber lease familiarity, Trading-specific FPGA solutions (Exegy, Arista, Efinix)
Technologies
FPGA, DPDK, Open Onload, FIX, Simple Binary Encoding, Exegy, Redline, NYSE, NASDAQ
Responsibilities
Design foundational messaging layer and evaluate protocol trade-offs; Architect FPGA-based acceleration for latency-critical paths; Design kernel bypass and OS-level optimization strategies; Architect sequencer and event stream design for deterministic recovery; Design ultra-low-latency market data ingestion layer; Lead design of Direct Market Access engine; Design normalized order entry and venue integration abstraction; Design risk enforcement architecture with hardware acceleration; Architect failover, replication, and deterministic recovery strategies; Design network infrastructure and colocation optimization; Design monitoring and observability infrastructure; Implement performance optimizations (CPU pinning, lock-free structures, NUMA awareness, SIMD).
Seniority
Director, Strategy & Hands-on IC
