Design Architecture, Principal Engineer
Core
Drive exploration and definition of next-generation AI memory and system environments by analyzing infrastructure trends and building performance models.
Role type
Principal HBM Design Architecture Engineer
Builds
Simulation frameworks, performance models, and trend dashboards for AI cluster and memory subsystem behavior
Domain
Semiconductor manufacturing, High Bandwidth Memory (HBM), AI infrastructure
Deliverable
production ML models | product features
Required skills
HBM/DDR/cache memory subsystem design, AI/ML workload analysis, Fab & Foundry experience, multi-disciplinary hardware knowledge, simulation framework development, performance modeling (bandwidth/latency), stakeholder alignment
Preferred skills
Microelectronic manufacturing advances, trade-off analysis, roadmap implication assessment
Technologies
HBM, DDR, caches, AI clusters, simulation frameworks
Responsibilities
Research and synthesize emerging trends in compute, networking, and storage infrastructure; Lead HBM architecture analysis by defining bandwidth/latency targets; Develop and maintain simulation frameworks to model AI cluster performance; Build first-order performance models spanning memory hierarchy trade-offs; Create and curate trend dashboards using industry datasets; Partner across teams to define architectural intercept opportunities and influence roadmaps
Seniority
Principal, hands-on IC with strategic influence
