OMT RAM RDA Process Optimization Engineer
Core
Using process and defect simulation methodologies to identify defect root causes and enable process window optimization in semiconductor manufacturing.
Role type
Process Optimization Engineer (Semiconductor Yield Engineering)
Builds
High-performance DRAM, NAND, and NOR memory and storage products
Domain
Semiconductor manufacturing / Yield engineering
Deliverable
production ML models | product features
Required skills
Process defect root cause analysis, process simulation modeling, manufacturing data analysis, statistical problem-solving (FA, FMEA, DOE, SPC, 8D), cross-functional technical communication
Preferred skills
Advanced process/physical modeling and simulation tools (TCAD, statistical modeling), yield modeling, defect density analysis, semiconductor change management, risk assessment
Technologies
TCAD, process simulation tools, statistical modeling software, inline metrology systems, defect inspection tools
Responsibilities
Develop and apply process/defect simulation models to understand defect generation mechanisms; Correlate simulation results with inline defect, EBI, process data, and yield indicators; Drive data-backed process optimization strategies to expand process windows; Perform what-if simulations to evaluate impact of process parameter changes; Partner with process, integration, and equipment engineers to translate insights into fab actions; Lead or support defect reduction, yield improvement, and cost reduction projects; Support new process introduction (NPI) and baseline qualification by assessing defect risks
Seniority
Mid-level to Senior, hands-on IC
