Sr Engineer - DEMQRA WLR
Core
Process reliability testing and analysis to support new product qualification, periodic monitoring, and HVM fab process conversion for advanced CMOS and interconnect scaling.
Role type
Senior IC Wafer Level Reliability Engineer
Builds
Reliability models, test methodologies, and risk mitigation strategies for memory and storage products
Domain
Semiconductor manufacturing / Memory and storage
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Wafer and package level reliability testing, failure mode analysis, statistical quality control, CMOS device engineering, process integration, risk assessment, data analysis
Preferred skills
Experience with parametric analyzers, semiconductor characterization, JEDEC standards compliance
Technologies
CMOS, Interconnects, JEDEC standards
Responsibilities
Perform wafer and package level reliability testing and analysis, comprehend failure modes and rates, assess risks at decision points, support HVM fab process conversion, collaborate on new technology node deployment, develop process reliability tests
Seniority
Senior, hands-on IC
