ENGINEER, OMT RAM RDA PROCESS
Core
Identify yield gain opportunities, implement baseline improvement programs, and qualify new processes to reduce scrap and excursions in semiconductor manufacturing.
Role type
Senior IC process engineer (yield management & defect analysis)
Builds
High-performance DRAM, NAND, and NOR memory and storage products
Domain
Semiconductor manufacturing (memory and storage)
Deliverable
production ML models | product features
Required skills
yield management, process control charting, defect analysis, contamination qualification, process characterization, conversion qualification, scrap reduction, defect library management, AI tool integration
Preferred skills
AI-enabled enhancement identification, digital fluency, baseline AI literacy
Technologies
process control charts, defect libraries, AI-assisted tools
Responsibilities
Identify yield gain opportunities and implement strategies to achieve yield targets; Plan and implement baseline improvement programs; Ensure accurate setup of process control charts; Collaborate with Process Integration and Production to meet goals; Follow up on SWR defects and update the defect library; Set up contamination, defect, and performance qualification procedures; Characterize process responses to parameters and define process margins; Qualify conversions and new processes to reduce scrap; Study new methods for defect analysis.
Seniority
Senior, hands-on IC
