SMTS Process Engineer, RET OPC
Core
Developing and optimizing Resolution Enhancement Techniques (RET) and Optical Proximity Correction (OPC) solutions to enable high-fidelity wafer patterning for advanced memory technologies.
Role type
Senior Member of Technical Staff, RET/OPC Process Engineer
Builds
Innovative reticle solutions, tapeout methodologies, and lithography optimization for next-gen memory and storage products
Domain
Semiconductor manufacturing, lithography, mask development
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RET/OPC methodologies, EUV lithography fundamentals, lithography simulation tools, root cause analysis, strategic technical direction, cross-disciplinary collaboration
Preferred skills
EDA software for OPC modeling, scripting languages (Python, Perl, TCL, C, C++), mentoring junior engineers
Technologies
Sentaurus Litho, ProLith, Synopsys, Siemens, Cadence, Brion
Responsibilities
Drive sophisticated projects in mask development and lithography optimization; Develop and implement RET/OPC solutions to improve pattern fidelity and yield; Investigate and deploy innovative methodologies to improve lithography performance; Guide strategic directions and interpret customer needs; Analyze patterning issues across R&D and manufacturing environments; Mentor junior engineers and nurture technical best practices
Seniority
Senior, hands-on IC with strategic direction