Memory IP Design Engineer- (eFuse/MTPM/OTP/MRAM/SRAM)
Core
Design, simulation, and verification of custom memory IP blocks (decoders, sense amplifiers, write drivers) for semiconductor foundry processes.
Role type
Senior IC analog/mixed-signal memory design engineer
Builds
Custom memory IP blocks (eFuse, MTPM, OTP, MRAM, SRAM)
Domain
Semiconductor manufacturing / Memory technology
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
full custom circuit design, statistical analysis, timing characterization, NVM memory design, EDA tools (Cadence, Mentor Graphics, Synopsys), analog mixed-signal concepts
Preferred skills
knowledge of Bulk/CMOS/SOI processes, design flow automation, 45nm/32nm/28nm technology nodes
Technologies
Virtuoso, Spectre, HSPICE
Responsibilities
Circuit design, simulation, and characterization of full custom circuits; Functional simulations and statistical analysis; Sign off and release memory IP on validation test chips; Support Silicon bring-up and characterization; Participate in implementation and design/layout reviews
Seniority
Senior, hands-on IC
