IP Silicon Validation Engineer
Core
Planning, validation, and debug of hardware IP for AMD APU, CPU, Compute, and Discrete Graphics SOC programs.
Role type
IP Validation Design Engineer
Builds
AMD APU, CPU, Compute, and Discrete Graphics SOC programs
Domain
Semiconductor / Processor Architecture
Required skills
ASIC debug techniques, high-speed interface protocols (PCIe/CXL/UALINK), board/platform-level debug, scripting (Ruby/Python), lab equipment usage (logic analyzers, oscilloscopes), system architecture/debug knowledge
Preferred skills
Digital logic design/verification, post-silicon validation, leadership and mentoring, technical innovation in validation tools/methodologies
Technologies
PCIe, CXL, UALINK, Ruby, Python, Logic Analyzers, Oscilloscopes
Responsibilities
Define and execute functional test plans and validation strategies, debug IP issues across pre-silicon to production phases, engage in pre-silicon shift-left activities with DV and emulation teams, lead technical discussions for issue resolution, support customer platform issues
Seniority
Mid-Senior, hands-on IC
