NPU Compiler Engineer
Core
Design and optimize compiler passes in the MLIR framework to compile and optimize AI workloads for AMD's NPU-based hardware.
Role type
Senior IC compiler engineer (AI/ML)
Builds
Next-generation compiler tools for Vitis-AI and Ryzen-AI software platforms
Domain
AI/ML compilers and NPU hardware acceleration
Deliverable
production ML models
Required skills
C++, Python, MLIR optimization and lowering passes, compiler architecture, NPU architecture, debugging with SystemC/RTL simulators
Preferred skills
AI compilers, tensor/graph compilers, machine learning frameworks, data-driven optimization
Technologies
MLIR, Vitis-AI, Ryzen-AI, SystemC, RTL simulators
Responsibilities
Enhance and implement compiler passes in MLIR for NPU optimization; Analyze and debug functional and performance issues; Build infrastructure for regression suite analysis; Apply AI and coding agents to development and debugging; Research efficient alternative implementations
Seniority
Senior, hands-on IC
