Distinguished Engineer, End-to-End Scaling Performance Architecture
Core
Define long-term performance strategy for scaling accelerated computing systems from single processors to multi-die, multi-GPU, and multi-node platforms, focusing on DRAM, NVLink, and chip-to-chip interconnects.
Role type
Distinguished Engineer (Strategy & Architecture)
Builds
Future generations of high-performance computing systems (AI, HPC, accelerated computing)
Domain
Hardware/Systems Architecture (High-Performance Computing, Accelerated Computing)
Deliverable
production ML models
Required skills
System performance scaling, DRAM behavior analysis, high-bandwidth fabric design (NVLink), chip-to-chip interconnects, application-level intuition, workload characterization, performance modeling, bottleneck analysis, architecture trade-off evaluation, cross-domain opportunity identification, technical strategy formulation, executive communication, mentorship
Preferred skills
Product roadmap shaping, quantitative bottleneck understanding, end-to-end performance improvement delivery
Technologies
DRAM, NVLink, C2C interconnects, GPUs, CPUs, software stacks
Responsibilities
Define multi-generation strategy for application scaling; Translate application behavior into architectural requirements and investment priorities; Evaluate system-level trade-offs across bandwidth, latency, topology, power, and cost; Establish workload scenarios and decision frameworks; Identify architectural discontinuities and emerging technology opportunities; Mentor system performance architects and build technical communities.
Seniority
Distinguished, Strategy & Mentorship
