Sr. IC Packaging Test Engineer, Silicon Technology (Starlink)
Core
Develop and release production test solutions for integrated circuit packaging and wafer level testing to ensure product conformance for Starlink satellite hardware.
Role type
Senior IC Packaging Test Engineer (Silicon Technology)
Builds
Production test equipment and automated test programs (ATE) for semiconductor packaging and wafer sort
Domain
Semiconductor manufacturing, satellite hardware, integrated circuit packaging
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
C/C++/Python programming, electrical test equipment definition, ATE test program creation, semiconductor packaging knowledge, wafer test expertise, schematic and electrical review, supplier test interface
Preferred skills
Microelectronics packaging development, high-speed and RF semiconductor test programs, SERDES testing, wafer probe and probe card design, custom socket design, functional and parametric test design
Technologies
C, C++, Python, ATE, SERDES, RF test equipment
Responsibilities
Own electrical test equipment definition for packaging and wafer level production testing, Bring-up of test equipment and test programs for mass manufacturing, Create automated test equipment (ATE) test programs and test plans, Define full and comprehensive testing requirements to ensure product conformance, Schematic and electrical review for all test equipment, Supplier test interface for implementing new features, cost, and productivity improvements
Seniority
Senior, hands-on IC
