Technical Lead - System Validation Architect
Core
Lead architecture and execution of Linux-based validation frameworks for Arm-based data center SoCs, defining strategy, test coverage, and methodology across CPU, memory, interconnect, and high-speed I/O subsystems.
Role type
Senior Technical Lead, System Validation Architect
Builds
Scalable validation methodologies and comprehensive system enablement for next-generation AI compute platforms
Domain
Hardware systems engineering, AI compute infrastructure, Arm SoC architecture
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Arm SoC architecture knowledge, Linux systems expertise, CPU architecture and cache coherency understanding, memory systems (DDR, HBM, NUMA), high-speed I/O (PCIe), validation strategy definition, benchmarking tool tuning (stress-ng, fio, iperf), Python programming for automation, performance analysis (perf, PMU counters), multi-core and parallel programming
Preferred skills
Large-scale data center systems experience, C/C++ programming, technical leadership and mentoring, scalable validation infrastructure frameworks, AI infrastructure or hyperscale compute systems knowledge
Technologies
Linux, Arm SoC, stress-ng, fio, iperf, Python, perf, PMU counters, PCIe, DDR, HBM, NUMA
Responsibilities
Define end-to-end validation strategy and coverage model (functional, stress, performance, corner-case testing); Translate hardware specifications into structured, parameterized test plans; Guide team in selecting tools and defining workload models; Establish standards for test case definition and result validation; Collaborate with hardware, firmware, and system teams to debug issues
Seniority
Senior, hands-on IC with leadership responsibilities
