Process Engineer III – (E3)
Core
Designing and optimizing manufacturing processes for display and semiconductor technologies, specifically next-generation thin-film deposition and surface treatment for advanced logic interconnect.
Role type
Senior IC process engineer (semiconductor/display)
Builds
300 mm chamber processes and hardware qualification
Domain
Semiconductor manufacturing / Materials science
Required skills
DOE design, wafer run execution, metrology, thin-film characterization, plasma processing, root-cause analysis, hardware bring-up, cross-functional collaboration
Preferred skills
None stated
Technologies
300 mm chambers, deposition tools, plasma tools, metrology equipment
Responsibilities
Own experiments end to end from DOE design through analysis; Develop and optimize deposition and plasma-based processes; Characterize films using standard thin-film metrology; Partner with mechanical, electrical, and RF engineering teams; Support new hardware bring-up, qualification, and chamber troubleshooting; Plan and run multiple experiment tracks in parallel
Seniority
Mid-level (0-3 years PhD or 2-5 years MS)