Member of Technical Staff, TPU Performance Engineering
Core
Build and optimize TPU backends, compiler integrations, runtime paths, and benchmarking infrastructure to make vLLM a first-class inference engine on Google TPUs.
Role type
Senior IC TPU performance engineer (ML inference systems)
Builds
Production-relevant model serving on TPU with clear correctness, latency, and throughput benchmarks
Domain
AI inference systems, TPU hardware, compilers, and ML kernels
Deliverable
production ML models
Required skills
TPU workload optimization, JAX, XLA, Pallas, ML kernel optimization, performance profiling, benchmarking, memory behavior analysis, compilation constraints
Preferred skills
vLLM, SGLang, TensorRT-LLM, XLA-based serving, batching, KV cache, decoding, compiler technologies (MLIR, LLVM), quantization methods (INT8, FP8, mixed precision)
Technologies
JAX, XLA, Pallas, vLLM, SGLang, TensorRT-LLM, MLIR, LLVM
Responsibilities
Build and optimize TPU backends, integrate compilers, optimize runtime paths, create benchmarking infrastructure, profile and measure performance, optimize ML kernels (attention, GEMM, sampling, KV cache)
Seniority
Senior, hands-on IC
