大模型框架专家（存算与AI） - 芯片研发
Core
Design and optimize cloud-side large model training and inference frameworks for in-memory computing (存算一体) AI chips to break the 'memory wall' and improve energy efficiency.
Role type
Senior IC large model framework expert (in-memory computing architecture)
Builds
High-efficiency AI chips and distributed training/inference frameworks for cloud-scale AI workloads
Domain
Semiconductor hardware design + Large Language Model (LLM) systems
Deliverable
production ML models
Required skills
C++/Python development, distributed training (data/tensor/pipeline/context parallelism), inference engine optimization (Paged Attention, Prefix Cache, speculative decoding), MoE training/inference, hardware-software co-design, AI compilers/runtime integration, low-precision quantization (FP8/INT8/INT4), CUDA/ROCm/NPU kernel development, NCCL/RDMA communication
Preferred skills
Experience with Megatron-LM, DeepSpeed, PyTorch FSDP, vLLM, SGLang, TensorRT-LLM, FP8/INT8/INT4 quantization, GPU/NPU cluster optimization
Technologies
PyTorch, JAX, Megatron-LM, DeepSpeed, PyTorch FSDP, vLLM, SGLang, TensorRT-LLM, CUDA, ROCm, NCCL, RDMA
Responsibilities
Architect and develop cloud-side LLM training/inference frameworks for in-memory chips; Optimize distributed training capabilities (parallelism, storage management, communication overlap); Develop and optimize LLM inference engines (Paged Attention, Prefix Cache, speculative decoding); Optimize MoE model training/inference efficiency; Participate in hardware-software co-design for compute/storage/interconnect; Collaborate on end-to-end precision calibration and performance optimization with compiler/hardware teams.
Seniority
Senior, hands-on IC
