芯片SLT测试工程师-芯片研发（深圳）
Core
Design and execute System Level Test (SLT) plans for CPU and AI SoC chips, including functional, performance, compatibility, and reliability testing.
Role type
Senior IC chip SLT test engineer
Builds
Production-ready SoC chips for consumer and enterprise markets
Domain
Semiconductor / Chip Design
Required skills
C/C++/Python/Java programming, SLT test case design, SoC system-level debugging, FA analysis, PCIe/DDR/JTAG/I2C/UART/SPI interface testing, mass production test environment deployment
Preferred skills
Experience with large SoC architectures, silicon pre/post-package test flow knowledge
Technologies
C, C++, Python, Java, PCIe, DDR, JTAG, I2C, UART, SPI
Responsibilities
Collaborate with EVB engineers to define SLT test schemes for CPU/AI SoCs; Design SLT test cases covering functional, performance, compatibility, and reliability; Debug and deploy SLT software/hardware environments to factory; Analyze SLT results to identify and report system-level defects; Assist in Failure Analysis (FA) for defective chips; Maintain mass production SLT test environments and data.
