Sr Engineer, Compiler
Core
Lead AI compiler architecture and code generation to optimize AI workloads (perception, sensor fusion, in-vehicle assistants) for Renesas next-generation automotive System-on-Chip platforms.
Role type
Senior IC AI Compiler Engineer
Builds
Optimized AI execution on Renesas 3 nm automotive SoCs (e.g., R-Car X5H) for ADAS, IVI, and SDV applications
Domain
Automotive semiconductor / AI hardware acceleration
Deliverable
production ML models
Required skills
AI compiler architecture, graph optimization, NPU performance tuning, MLIR/LLVM/TVMS, C/C++, Python, AI inference workloads
Preferred skills
automotive safety-critical systems, heterogeneous SoC design, hardware-software co-design
Technologies
MLIR, LLVM, TVM, C++, Python
Responsibilities
Lead AI compiler architecture across model ingestion, graph optimization, lowering, and code generation; Design and implement graph-level optimizations (operator fusion, quantization-aware rewrites, memory-aware scheduling); Drive performance optimization for target NPUs (tiling, tensor layout, multi-core strategies); Partner with SoC and AI accelerator architects to influence hardware features; Own performance KPIs for real automotive AI workloads using simulators and profilers; Ensure compiler outputs meet automotive real-time and determinism requirements; Mentor senior engineers and set technical direction
Seniority
Senior, hands-on IC
