Sr Staff Engineer, Compiler
Core
Lead AI compiler architecture and code generation to optimize AI workloads (perception, sensor fusion, in-vehicle assistants) for Renesas next-gen automotive System-on-Chip platforms.
Role type
Sr Staff Engineer, AI Compiler
Builds
Optimized code for Renesas 3 nm automotive SoCs (R-Car X5H) running ADAS, IVI, and SDV workloads.
Domain
Automotive semiconductor / AI inference / Compiler technology
Deliverable
production ML models
Required skills
AI compiler architecture, graph optimization (operator fusion, quantization-aware rewrites, memory-aware scheduling), NPU performance optimization (tiling, tensor layout), C/C++, Python, AI inference workloads (CNNs, transformers)
Preferred skills
Automotive/safety-critical systems, heterogeneous SoCs, hardware-software co-design
Technologies
MLIR, LLVM, TVM-like systems, proprietary compiler IRs
Responsibilities
Lead AI compiler architecture across model ingestion, graph optimization, lowering, code generation, and runtime integration; Design and implement graph-level optimizations; Drive performance optimization for target NPUs; Partner with SoC and AI accelerator architects; Own performance KPIs for real automotive AI workloads; Ensure compiler outputs meet automotive requirements; Mentor senior engineers and set technical direction
Seniority
Sr Staff, hands-on IC with mentorship
