Senior Microarchitecture Researcher
Core
Design and simulate physical layouts for fault-tolerant ion trap quantum processors and quantum error correction protocols.
Role type
Senior IC microarchitecture researcher (quantum hardware)
Builds
Physical layouts for ion trap quantum chips and simulation tools for logical performance analysis
Domain
Quantum computing hardware / Ion trap architecture
Required skills
Quantum error correction (QEC) theory, AMO theory, classical VLSI theory, quantum simulation techniques, logical operations and decoders
Preferred skills
Experience with quantum chip architecture, trap design collaboration
Technologies
Ion trap processors, simulation tools
Responsibilities
Contribute to physical implementation of quantum error correction protocols on ion trap processors; Contribute to a library of simulation tools that analyze logical performance under realistic physical noise models; Collaborate with trap designers, AMO physicists, and QEC researchers; Contribute to research papers and technical writing
Seniority
Senior, hands-on IC
