Distinguished PQC Cryptography & Architecture Leader
Core
Define end-to-end architecture and technical roadmap for a post-quantum cryptography (PQC) hardware acceleration product line targeting HSM and network-appliance applications.
Role type
Distinguished PQC Cryptography & Architecture Leader
Builds
FPGA-based PQC accelerators with a clear path to ASIC for hardware security modules and network appliances
Domain
Quantum-safe security, cryptography, hardware architecture
Deliverable
production ML models | product features
Required skills
PQC algorithm design (ML-KEM, ML-DSA, SLH-DSA/LMS), FPGA microarchitecture, cryptographic standards strategy (NIST FIPS 203/204/205, CNSA 2.0, FIPS 140-3), hardware/firmware partitioning, side-channel security, IP licensing strategy
Preferred skills
ASIC design experience, lattice-based cryptography expertise, timing closure optimization
Technologies
FPGA, ASIC, ML-KEM, ML-DSA, SLH-DSA, LMS
Responsibilities
Define system and microarchitecture for multi-algorithm PQC accelerators; own algorithm and standards strategy; drive make/buy and IP-licensing decisions; shape security and certification architecture; set technical roadmap and mentor senior engineers; represent the programme externally with customers and standards bodies
Seniority
Distinguished, strategic technical authority with mentorship responsibilities