Senior QPU Design Engineer
Core
Senior IC design engineer responsible for translating operational requirements into chip layouts for high-performance ion trap quantum processing units.
Role type
Senior IC design engineer (quantum hardware)
Builds
Ion trap chips with photonics and CMOS interfaces for utility-scale quantum computers
Domain
Quantum computing hardware / Semiconductor design
Deliverable
production ML models | product features | infrastructure
Required skills
Chip layout, multi-layer routing, metal track routing, photonics interface design, CMOS interface design, GDSFactory (Python), Cadence IC layout, ion trap design, IC packaging
Preferred skills
Scripted layout generation, cross-functional collaboration, project ownership
Technologies
GDSFactory, Python, Cadence
Responsibilities
Translate design requirements into chip layouts, guide chips through full design process to tape-out, collaborate with scientists to settle specifications, coordinate with teams for feasibility and compatibility, own delivery of final tape-out
Seniority
Senior, hands-on IC
