Photonic Layout Engineer
Core
Design and layout of photonic integrated circuits (PICs) for Quantum Processor Units (QPUs) to enable scaling to thousands of qubits.
Role type
Photonic Layout Engineer
Builds
High-performance ion trapping chips and quantum computing hardware
Domain
Quantum computing / Integrated Photonics
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Photonic Integrated Circuit (PIC) layout, Python scripting for mask generation, DRC/LVS verification, PDK contribution, photonic device principles (waveguides, beamsplitters, grating couplers)
Preferred skills
Custom layout generation for complex semiconductor devices, commercial simulation/verification environments (Synopsys, Cadence, Ansys), manufacturing process knowledge
Technologies
Luceda IPKISS, GDSFactory, Klayout, Python
Responsibilities
Arrange and route photonic components on multi-layer chips; produce reticle-size photonic layout files for tape-out; collaborate with scientists and fabrication engineers to define design rules; perform layout verification through DRC and LVS; contribute to custom layout Process Design Kits (PDKs); document layout processes and final tape-out mask files
Seniority
Mid-level, hands-on IC
