Senior Mask Layout Engineer
Core
Owner of full-reticle tapeouts for trapped-ion quantum computers, including photonic and analog electronic layers.
Role type
Senior IC mask layout engineer (quantum computing)
Builds
Integrated quantum computing systems for cloud providers and enterprise clients
Domain
Quantum computing / Semiconductor manufacturing / Integrated photonics
Deliverable
production ML models | product features | infrastructure
Required skills
Python-based mask layout (Luceda IPKISS, GDSFactory, Klayout), semiconductor manufacturing processes, physical verification (DRC, LVS, ERC), circuit layout libraries, version control, shell scripting
Preferred skills
M.S./Ph.D. in Photonics/Physics/EE, full-reticle tapeout ownership with commercial foundries, commercial simulation environments (Synopsys, Cadence, Ansys), photonic/analog device principles
Technologies
Luceda IPKISS, GDSFactory, Klayout, Synopsys, Cadence, Ansys
Responsibilities
Conduct Python-based layout for full-reticle tapeouts; Develop and maintain internal PCell and automated circuit layout libraries; Interface with designers, test engineers, packaging engineers, and foundry team; Implement physical verification checks of layouts; Develop detailed documentation of tapeouts and lead layout reviews; Work with cross-functional teams to understand circuit requirements and improve design workflows
Seniority
Senior, hands-on IC
