Deep Learning Compiler Engineer
Core
Design and implement algorithmic optimizations to lower and optimize neural networks on the Quadric EPU hardware architecture.
Role type
Senior IC deep learning compiler engineer
Builds
Optimized neural network inference workloads for edge and endpoint devices
Domain
Edge computing / Hardware-accelerated machine learning
Deliverable
production ML models
Required skills
algorithmic optimization, graph algorithms, deep neural networks, numerical optimization, C++
Preferred skills
TVM, compiler front-end/back-end techniques
Responsibilities
Drive lowering and optimization of deep neural networks, solve NP-hard optimization problems, develop algorithms for graph-based execution on Quadric architecture
Seniority
Senior, hands-on IC
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