STAGE – Etude et réduction de l’impact environnemental des dépôts DIEL – F/H
Core
Evaluate and reduce the environmental impact of dielectric deposition processes in semiconductor manufacturing.
Role type
Junior IC process engineer (eco-design)
Builds
Eco Score for deposition processes and optimized cleaning protocols
Domain
Semiconductor manufacturing / Environmental engineering
Required skills
Materials science, Environmental science, Semiconductor fabrication processes, Data analysis
Preferred skills
Programming, English (fluent)
Responsibilities
Analyze deposition processes to calculate environmental impact; Propose optimization for chamber cleaning to reduce environmental footprint
Seniority
Internship / Student (Master2 2026-2027)