Sr. Engineer, Performance Infrastructure (RISC-V)
Core
Build and run performance infrastructure (benchmarking automation, data collection, workload capture) across RISC-V silicon, FPGA/emulation, and performance models to enable performance and software engineers.
Role type
Senior Infrastructure Engineer (Performance)
Builds
Benchmarking automation, CI pipelines, performance data databases, dashboards, and workload replay tooling.
Domain
Semiconductor / CPU Performance / RISC-V
Deliverable
infrastructure
Required skills
Linux systems engineering, Python, shell scripting, CI/CD (GitLab), containerization, job scheduling, artifact management, database management, dashboarding, QEMU, CRIU
Preferred skills
CPU performance curiosity, microarchitecture knowledge
Technologies
RISC-V, FPGA, QEMU, CRIU, GitLab, SPEC
Responsibilities
Build and maintain benchmarking automation and CI pipelines; Own SimPoint generation and management infrastructure; Build performance-data collection into databases with visualization; Develop workload capture and replay tooling; Collaborate with performance and software engineers to remove infrastructure friction.
Seniority
Senior, hands-on IC
