Post-Silicon Lab Manager
Core
Manage post-silicon lab infrastructure and operational workflows for bring-up, system validation, and customer enablement of high-performance RISC-V CPU architectures and chiplet solutions.
Role type
Senior IC lab manager (semiconductor hardware)
Builds
First-silicon power-on, system bring-up, and platform validation environments for multi-core CPU and chiplet-based systems
Domain
Semiconductor hardware / CPU architecture / Post-silicon validation
Required skills
High-speed interface expertise (PCIe, DDR/GDDR/HBM, SerDes), board-level debug tools, lab infrastructure scaling, CapEx budget management, inventory and calibration cycle management, JIRA/Confluence proficiency
Preferred skills
Startup mindset, cross-functional communication, remote team alignment
Technologies
JIRA, Confluence, logic/protocol analyzers, traffic generators, data acquisition rigs, power telemetry rigs
Responsibilities
Run day-to-day lab operations for CPU post-silicon validation, power/performance assessment, and debug; Lead the lab environment for first-silicon power-on, system bring-up, and platform validation including board-level fixes; Deploy and maintain server racks, data acquisition, power telemetry rigs, and automated test benches; Manage CapEx budget for scopes, logic/protocol analyzers, and traffic generators; Own inventory, calibration cycles, silicon allocation tracking, and lab safety compliance
