Staff Engineer,Post-Silicon Validation
Core
Drive first-silicon bring-up, validation, and debug of RISC-V-based System-on-Chips (SoCs) from initial power-up to production readiness.
Role type
Staff Engineer, Post-Silicon Validation
Builds
High-performance RISC-V CPU-based SoCs and AI platforms
Domain
Semiconductor / Hardware Engineering / RISC-V Architecture
Deliverable
production ML models
Required skills
SoC bring-up, silicon debug, RISC-V privilege modes, bare-metal testing, Linux bring-up, hardware/software interaction debugging, interconnect validation, memory subsystem debugging, high-speed interface debugging
Preferred skills
Experience with AI accelerators, cross-functional collaboration, ECO validation
Technologies
RISC-V, SoC, Linux, bare-metal, high-speed interfaces
Responsibilities
Lead first-silicon bring-up of RISC-V CPU–based SoCs; Debug silicon issues across CPU cores, interconnects, memory subsystems, peripherals, and high-speed interfaces; Develop and debug bare-metal tests, boot flows, and collaborate on Linux bring-up and driver validation; Provide actionable feedback, support ECO validation, and drive fixes for future silicon revisions.
Seniority
Staff, hands-on IC
