Staff CPU Microarchitect, Vector and Matrix Compute
Core
Designing next-generation high-performance RISC-V CPU Vector (RVV), Floating Point, and Matrix extensions to enable efficient execution of HPC and AI inference/training workloads.
Role type
Staff CPU Microarchitect (Vector and Matrix Compute)
Builds
High-performance RISC-V CPU compute execution units and subsystems for HPC and AI platforms
Domain
Semiconductor / CPU Architecture / AI Acceleration
Deliverable
production ML models
Required skills
CPU architecture design, matrix floating-point computation, vector processing, heterogeneous compute systems, RTL development, memory hierarchy design, cache coherency, cross-functional team leadership
Preferred skills
Experience with cutting-edge AI frontier models, silicon implementation leadership
Technologies
RISC-V, RVV, RTL, HPC, AI accelerators
Responsibilities
Drive architecture and micro-architecture of compute execution units; translate HPC/AI workload requirements into scalable CPU architectures; optimize performance, power, and area (PPA); define architectural specifications and lead teams from concept to silicon; collaborate with software teams and silicon designers.
Seniority
Staff, hands-on IC with strategic influence
