Senior Engineer, System-Level Design Verification
Core
Validating full-system behavior, connectivity, and throughput for large distributed AI compute platforms to ensure reliable silicon performance.
Role type
Senior System-Level Design Verification Engineer
Builds
High-performance AI silicon platforms based on RISC-V architecture
Domain
AI hardware / Semiconductor / Distributed Compute Systems
Deliverable
production ML models | infrastructure
Required skills
Full-system verification, AI workload performance analysis, hardware-software debugging, observability framework design, system-level test strategy, distributed system validation
Preferred skills
RISC-V architecture knowledge, AI stack co-design experience, performance tuning expertise
Technologies
RISC-V, distributed compute platforms, AI workloads
Responsibilities
Validate system connectivity, coherency, and functionality across large distributed AI compute systems; Measure and tune performance for end-to-end AI workloads to hit silicon targets; Define and evolve observability, diagnostics, and system-level test frameworks; Align verification plans with silicon goals in partnership with hardware and software teams
Seniority
Senior, hands-on IC
