Manager, ATE Test Engineering
Core
Lead the Test Engineering organization to drive next-generation high-speed, high-performance connectivity products from silicon bring-up through high-volume manufacturing for rack-scale AI infrastructure.
Role type
Manager, ATE Test Engineering
Builds
Scalable ATE solutions for complex mixed-signal silicon products and high-speed connectivity chips (PCIe, Ethernet, NVLink, etc.)
Domain
Semiconductor / High-speed Connectivity / AI Infrastructure
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
ATE test strategy definition, team leadership, silicon bring-up, bench-to-ATE correlation, high-speed protocol knowledge (PCIe, Ethernet, DDR, NVMe, USB), DFT implementation (SCAN, MBIST, SerDes), production test optimization, hardware development (load boards, interface hardware), cross-functional partnership
Preferred skills
Wafer-sort and final-test hardware development, high-speed SerDes testing (>16 Gbps), C/C++ or Python for ATE programming and automation, RF testing on ATE platforms, advanced DFT control interfaces (I2C, I3C, SPI, MDIO, JTAG)
Technologies
Advantest 93k, Teradyne platforms, Protocol analyzers, Oscilloscopes, Manufacturing systems
Responsibilities
Build and mentor a high-performing ATE Test engineering team; Define end-to-end ATE test strategies and plans; Guide tester platform selection and development of load boards and interface hardware; Direct ATE program development, pattern implementation, and debug; Partner with design and DFT teams to maximize defect and parametric coverage; Use data from production and lab equipment to resolve issues and improve product quality
Seniority
Manager, hands-on IC leadership
