Senior ATE Test Engineer
Core
Lead ATE Test solutions for complex mixed-signal silicon SoC products from design through high-volume production ramp.
Role type
Senior ATE Test Engineer (SoC)
Builds
ATE test programs, hardware, and test strategies for rack-scale AI connectivity chips.
Domain
Semiconductor / High-speed connectivity (PCIe, Ethernet, NVLink, etc.)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
ATE test strategy definition, high-speed mixed-signal SoC test development, tester platform selection, high-speed load board design, DFT implementation (SCAN, MEMBIST, SerDes), ATE programming, silicon/ATE bring-up, bench-ATE correlation, debug, protocol analyzer/oscilloscope usage, Advantest 93k platform expertise, C/C++ or Python programming
Preferred skills
Data processing with high-level languages, external loopback at wafer sort, modern database familiarity
Technologies
Advantest 93k, C/C++, Python, PCIe Gen-4/5/6, Ethernet, Infiniband, DDR, NVMe, USB, I2C, I3C, SPI, MDIO, JTAG
Responsibilities
Develop and oversee SoC test strategy; define and implement ATE programs; select and develop ATE hardware for wafer sort and final test; implement ATE patterns to optimize resources and minimize test time; develop DFT techniques for maximum defect coverage; perform silicon/ATE bring-up and debug; collaborate with design teams on test plans.
Seniority
Senior, hands-on IC
