Senior Engineer, CAD Layout Automation
Core
Develop AI-assisted and automated workflows for the physical layout, verification, and design of CMOS integrated circuits to increase layout team productivity.
Role type
Senior IC CAD Layout Automation Engineer
Builds
Automated placement, routing, and optimization flows for memory layouts
Domain
Semiconductor manufacturing / Physical Design / EDA
Deliverable
production ML models
Required skills
Python, Tcl, Perl, Skill (Cadence), Linux, AI/ML frameworks (PyTorch, scikit-learn), LLM API integration, DRC/ERC/LVS/DFM debugging, CMOS process knowledge, EMIR/RC-Extraction/ESD/Latch-up understanding
Preferred skills
PDN analysis (Totem/VoltusXFA/XA), Agentic AI flows, Rule-aware automation
Technologies
Cadence Virtuoso, Synopsys Custom Compiler, Pulsic Unity, Itools, Calibre/ICV
Responsibilities
Evaluate and improve EDA tools and flows for physical layout and verification; Develop methodologies for reliable layout with faster Time to Market; Lead layout flows implementation using AI-assisted and automated workflows; Provide guidance and mentorship to junior team members; Integrate LLM APIs into engineering tools and workflows.
Seniority
Senior, hands-on IC