FY27 Intern - Hardware Design for Post-Quantum Cryptography - 6 months, Sophia
Based in France
Core
Design hardware accelerators for post-Quantum cryptography (PQC) algorithms to ensure future-proof security against quantum attacks.
Role type
Hardware Design Intern
Builds
Dedicated hardware accelerators for PQC
Domain
Cryptography / Hardware Security / SoC
Required skills
RTL Coding and Simulation, RSIC-V CPU architecture, Verilog/SystemVerilog, C, Assembly, Python, Linux, Bash, TCL, Git, Cadence/Synopsys/Mentor Graphic
Preferred skills
SoC/IP design knowledge, tooling and scripting, CAD environment familiarity
Responsibilities
Collaborate with architecture teams during specification phase, implement security concepts and techniques, develop hardware accelerators
Seniority
Intern
