FY27 Intern - HW/FW Architecture for Post-Quantum Cryptography - 6 months, Sophia
Core
Co-design hardware and firmware for post-quantum cryptography primitives, including efficient implementations on CPU cores and HW accelerators, and secure them against diverse attackers.
Role type
Intern, hardware/firmware architecture engineer (post-quantum cryptography)
Builds
Hardware and firmware implementations of post-quantum cryptography primitives
Domain
Cryptography, hardware security, mobile technologies
Required skills
Cryptography, C, Assembly, Python, Git
Preferred skills
Side-channel attacks, Embedded software development, CPU architecture, SoC/IP design, RTL coding, FPGA prototyping, Verilog, System Verilog
Technologies
Python, C, Assembly, Git, VHDL, Verilog, FPGA, Cadence, Synopsys, Mentor Graphics, Matlab, Bash
Responsibilities
Conduct literature review of post-quantum algorithms, develop efficient hardware and firmware implementations, model HW/SW platforms, build prototypes on FPGAs, optimize and secure implementations against attackers
Seniority
Intern
