FY27 Intern - CHERI-Based Prototype for Root of Trust Security - 6 months, Sophia
Core
Investigate HW/SW co-design techniques on CHERI-enabled RISC-V platforms to develop prototypes for Root of Trust (RoT) and secure-enclave requirements.
Role type
Intern, hardware/software co-design engineer
Builds
Practical prototypes for RoT and secure-enclave systems
Domain
Semiconductor, embedded security, RISC-V architecture
Required skills
C, C++, Rust, Verilog, System Verilog, Python, RTL coding, FPGA prototyping, SoC/IP design, compiler/linker knowledge, RTOS
Preferred skills
Embedded software development, CPU architecture, ASIC/FPGA EDAs (Xilinx Vivado, Cadence, Synopsis)
Responsibilities
Explore and demonstrate novel security concepts for memory safety and isolation; combine architecture exploration, RTL and software development, and security evaluation.
Seniority
Intern
