Firmware Engineer – SerDes PHY (all levels)
Core
Design, develop, and validate embedded firmware for high-performance SerDes PHY IP used in AI data centers, automotive, and compute applications.
Role type
Senior Firmware Engineer (SerDes PHY)
Builds
SerDes PHY IP integrated into SoCs, ASICs, and chiplets for next-generation data center and AI/ML applications
Domain
Semiconductor / Hardware / Data Center / AI
Deliverable
production ML models
Required skills
C, C++, Python, RISC-V, embedded firmware architecture, hardware calibration, DSP adaptations, link state management, protocol specifications (PCIe, Ethernet, CXL, UCIe), EDA tool integration, post-silicon bring-up and debug
Preferred skills
RTL/digital design phase experience, cross-functional team leadership, CI/CD infrastructure
Technologies
RISC-V, C, C++, Python, PCIe, Ethernet, CXL, UCIe, EDA tools
Responsibilities
Lead firmware architecture and development from pre-silicon design through post-silicon validation; Architect and implement embedded C/C++ firmware for hardware calibration, training algorithms, and link state management; Translate protocol specifications into internal firmware architecture; Debug complex lab and field issues in conjunction with hardware and validation teams; Coordinate execution across multiple teams and sites; Develop test and debug capabilities to guide hardware design decisions.
