PST Validation Engineer
Core
Perform silicon bring-up, measure post-silicon metrics (Vmin/Fmax, power, thermal), debug low-level software/hardware issues, manage emulation builds, and automate validation flows for high-performance SoC products.
Role type
Post-Silicon Validation Engineer (ASIC/SoC)
Builds
High-performance, low-power mobile chip products (SoC/IP)
Domain
Semiconductor / Mobile SoC Design
Required skills
Mobile chip architecture knowledge, RTL basics, transistor power fundamentals, regression/PVT testing, low-level debugging (JTAG, kernel debuggers), Python/C scripting, test bench infrastructure design
Preferred skills
Master's degree in EE/CS, architecture/design tools experience, scripting tools experience, design verification methods experience
Technologies
JTAG, Lauterbach Trace32, Python, C, RTL, PVT testing tools
Responsibilities
Perform silicon bring-up and characterize system-level data across PVTs; Debug low-level software and hardware issues using JTAG and kernel debuggers; Manage emulation builds, run tests, and collaborate with CAD/RTL/Design teams; Automate validation flows and data analysis using Python or similar scripting languages
Seniority
Mid-level IC Engineer