CAD RTL/DV Infrastructure Engineer, Staff
Core
Build and maintain CI/CD infrastructure and automation for CPU design and verification workflows.
Role type
Staff IC infrastructure engineer (CPU verification)
Builds
CI/CD pipelines, verification flows, and design environments for Oryon CPU
Domain
Semiconductor hardware engineering (CPU design and verification)
Deliverable
infrastructure
Required skills
Git, GitHub, Python, Shell scripting, LSF (Load Sharing Facility), Jenkins, Airflow, CI/CD principles, infrastructure management, problem-solving
Preferred skills
RTL design (Verilog/SystemVerilog), CPU microarchitecture, verification methodologies, Perforce, Splunk dashboards
Technologies
Git, GitHub, Jenkins, Airflow, LSF, Python, Shell scripting, Perforce, Splunk
Responsibilities
Maintain and enhance CI/CD infrastructure for CPU design and verification workflows; Partner with RTL, DV, and DFT teams to optimize verification flows; Drive automation and continuous improvement initiatives; Collaborate with global teams to ensure alignment and scalability; Work with EDA tool vendors to resolve tool-related issues; Troubleshoot and resolve issues in design and verification environments.
