Principal Engineer, RET Design
Core
Develop and optimize Resolution Enhancement Techniques (RET) and Optical Proximity Correction (OPC) solutions to enable high-fidelity wafer patterning for advanced memory technologies.
Role type
Principal Engineer, RET Design (IC)
Builds
Reticle solutions and lithography optimization projects for next-generation memory and storage products
Domain
Semiconductor manufacturing, lithography, materials science
Required skills
RET and OPC methodologies, EUV lithography, optics, diffraction, resist behavior, lithography simulation tools (Sentaurus Litho, ProLith)
Preferred skills
EDA tools (Synopsys, Siemens, Cadence, Brion), Python/Perl/TCL/C/C++ scripting, semiconductor process development, engineering mentorship
Technologies
Sentaurus Litho, ProLith, Synopsys, Siemens, Cadence, Brion
Responsibilities
Develop and implement RET and OPC solutions to improve pattern fidelity and yield; Optimize lithography methodologies and tapeout processes; Analyze patterning issues and drive corrective actions; Lead complex mask development projects; Mentor engineers and promote technical best practices
Seniority
Principal, hands-on IC with mentorship